*
What is a ESD ?
ESD is defined as the sudden transfer of electrical charge between objects at different electrostatic potentials [1, 2] Also called Zap.
What is a ZAP ?
A cause of sudden moves of rapidly charged particles in a specific direction
HBM
The first one is the Human Body Model (HBM), which simulates the direct contact of a charged human body and a component.
CDM
The second is the Charged Device Model (CDM), which simulates the contact between a charged component with another component.
The major difference between these two models is the rise-time and the fall time of the ESD current pulse.
The HBM current waveform has typically a rise-time less than 10 ns and fall time between 50 and 300 ns.
The CDM current waveform has typically a risetime and fall time below 1 ns and 10 ns respectively [10].
ESD is defined as the sudden transfer of charge between objects at different electrostatic potentials [1, 2]. Electrostatic discharge can change the electrical characteristics of a semiconductor device, degrading or destroying it. Electrostatic discharge also may upset the normal operation of an electronic system, causing equipment malfunction or failure.
Electrostatic charge is created whenever two different materials comes into contact and are then separated. Creating electrostatic charge by contact and separation of materials is known as “triboelectric effect”. It involves the transfer of electrons between materials. The atoms of a material with no static charge have an equal number of positive (+) protons in their nucleus and negative (-) electrons orbiting the nucleus. For example, a person walking across the floor generates static electricity as shoe soles contact and then separate from the floor surface. The charge is transferred between objects normally via a spark when the potential across the narrowing air gap is high enough to cause breakdown [3, 4].
It is obvious that ESD is a transient overvoltage pulse with a steep rising edge, a high current amplitude but low energy content. A considerable amount of effort has been made to study ESD current waveforms and it has been shown that the amplitudes and risetimes vary with
Standard EN 61000-4-2, ESD generators, ESD
the charging voltages, approach speeds, electrode types and humidity [5-7].
A wide variety of engineering models have been proposed to simulate electrostatic discharge events but in general they fall into two categories [8, 9].
Rules for the protection strategy of an integrated circuit
During the design of the global ESD protection strategy of the IC, the ground rules are:
Rules for the protection strategy of an integrated circuit
Rules for the protection strategy of an integrated circuit
Rules for the protection strategy of an integrated circuit
During the design of the global ESD protection strategy of the IC, the ground rules are:
– each pin must have at least one ESD protection, with the exception of selfprotected pins;
– there must be a discharge path between all of the couples of the pins and for different polarities, positive and negative.
Another aspect involves the sizing of the protection, as well as its placement and associated routing:
– the sizing of the protection is conditioned by the value of its on-resistance RON. The silicon footprint of the protection depends in part on the targeted ESD robustness, keeping in mind the impact of the operating temperature on the value of RON;
– the resistors in these protections are usually made of polysilicon to avoid the formation of any parasitic components. However, it is important to size them correctly, making sure that the current capability does not become the weak link of the protection;
– the same precaution must be applied to the metallic rails whose routing must be as short and simple as possible, so as to avoid the effects of high current densities and of localized thermal heating;
– the placement and number of contacts and vias must also be carried out carefully, checking their respective current capability;
– in digital technologies, the ESD pads are already available, and placement is therefore pre-imposed. In mixed and analog technologies, each new circuit requires a new approach for protection.
Careful attention must be paid to the placement of ESD protections to avoid the formation of parasitic structures with certain blocks of the circuit;
During the design of the global ESD protection strategy of the IC, the ground rules are:
– each pin must have at least one ESD protection, with the exception of selfprotected pins;
– there must be a discharge path between all of the couples of the pins and for different polarities, positive and negative.
Another aspect involves the sizing of the protection, as well as its placement and associated routing:
– the sizing of the protection is conditioned by the value of its on-resistance RON. The silicon footprint of the protection depends in part on the targeted ESD robustness, keeping in mind the impact of the operating temperature on the value of RON;
– the resistors in these protections are usually made of polysilicon to avoid the formation of any parasitic components. However, it is important to size them correctly, making sure that the current capability does not become the weak link of the protection;
– the same precaution must be applied to the metallic rails whose routing must be as short and simple as possible, so as to avoid the effects of high current densities and of localized thermal heating;
– the placement and number of contacts and vias must also be carried out carefully, checking their respective current capability;
– in digital technologies, the ESD pads are already available, and placement is therefore pre-imposed. In mixed and analog technologies, each new circuit requires a new approach for protection.
Careful attention must be paid to the placement of ESD protections to avoid the formation of parasitic structures with certain blocks of the circuit;
Excerpt from: “ESD Protection Methodologies: From Component to System” by Marise Bafleur. Scribd.
Read this book on Scribd: https://www.scribd.com/book/354928445
Art.S 